1. Field of the Invention
The present invention relates to a nonvolatile semiconductor storage apparatus including memory cells each having a plurality of thresholds.
2. Background Art
Recent nonvolatile semiconductor storage apparatuses use a multivalued technique for providing each memory cell with a plurality of threshold states to allow the memory cell to store plural bits of information, increasing the capacity of the memory cell (see, for example, Japanese Patent Laid-Open No. 2000-195280). This technique has reduced the difference between adjacent thresholds.
Thus, a defect in the memory cell or an excessive applied write voltage may cause the thresholds for the memory cell to be erroneously written to positions different from the desired ones. This is likely to cause erroneous write operations.
In particular, a threshold voltage adjacent to the correct one is frequently erroneously written to the memory cell. An external error correction circuit is thus introduced to correct erroneously written threshold voltage during a read operation. However, a variation in error rate among pages may hinder errors from being efficiently corrected. Thus, desirably, the fraction defectives of the respective pages are made as uniform as possible.
Further, with a conventional read procedure, the multivalued memory cell significantly varies the time required to read each of plural bits. This may affect the amount of time before data can be output. Accordingly, the read time needs to be averaged.